FSP Configuration
  Board "Custom User Board (Any Device)"
  R7FA4M2AD3CFP
    part_number: R7FA4M2AD3CFP
    rom_size_bytes: 524288
    ram_size_bytes: 131072
    data_flash_size_bytes: 8192
    package_style: LQFP
    package_pins: 100
    
  RA4M2
    series: 4
    
  RA4M2 Family
    Enable inline BSP IRQ functions: Enabled
    Security: Exceptions: Exception Response: Non-Maskable Interrupt
    Security: Exceptions: BusFault, HardFault, and NMI Target: Secure State
    Security: System Reset Request Accessibility: Secure State
    Security: Exceptions: Prioritize Secure Exceptions: Disabled
    Security: Cache Accessibility: Both Secure and Non-Secure State
    Security: System Reset Status Accessibility: Both Secure and Non-Secure State
    Security: Battery Backup Accessibility: Both Secure and Non-Secure State
    Security: SRAM Accessibility: SRAM Protection: Both Secure and Non-Secure State
    Security: SRAM Accessibility: SRAM ECC: Both Secure and Non-Secure State
    Security: SRAM Accessibility: Standby RAM: Regions 7-0 are all Secure.
    Security: BUS Accessibility: Bus Security Attribution Register A: Both Secure and Non-Secure State
    Security: BUS Accessibility: Bus Security Attribution Register B: Both Secure and Non-Secure State
    Security: Uninitialized Non-Secure Application Fallback: Enable Uninitialized Non-Secure Application Fallback
    Startup C-Cache Line Size: 32 Bytes
    OFS0 register settings: Independent WDT: Start Mode: IWDT is stopped after a reset
    OFS0 register settings: Independent WDT: Timeout Period: 2048 cycles
    OFS0 register settings: Independent WDT: Dedicated Clock Frequency Divisor: 128
    OFS0 register settings: Independent WDT: Window End Position:  0% (no window end position)
    OFS0 register settings: Independent WDT: Window Start Position: 100% (no window start position)
    OFS0 register settings: Independent WDT: Reset Interrupt Request Select: Reset is enabled
    OFS0 register settings: Independent WDT: Stop Control: Stop counting when in Sleep, Snooze mode, or Software Standby
    OFS0 register settings: WDT: Start Mode Select: Stop WDT after a reset (register-start mode)
    OFS0 register settings: WDT: Timeout Period: 16384 cycles
    OFS0 register settings: WDT: Clock Frequency Division Ratio: 128
    OFS0 register settings: WDT: Window End Position:  0% (no window end position)
    OFS0 register settings: WDT: Window Start Position: 100% (no window start position)
    OFS0 register settings: WDT: Reset Interrupt Request: Reset
    OFS0 register settings: WDT: Stop Control: Stop counting when entering Sleep mode
    OFS1_SEL register settings: Voltage Detection 0 Level Security Attribution: VDSEL setting loads from OFS1_SEC
    OFS1_SEL register settings: Voltage Detection 0 Circuit Start Security Attribution: LVDAS setting loads from OFS1_SEC
    OFS1 register settings: Voltage Detection 0 Circuit Start: Voltage monitor 0 reset is disabled after reset
    OFS1 register settings: Voltage Detection 0 Level: 2.80 V
    OFS1 register settings: HOCO Oscillation Enable: HOCO oscillation is disabled after reset
    Block Protection Settings (BPS): BPS0: 
    Permanent Block Protection Settings (PBPS): PBPS0: 
    Clocks: HOCO FLL Function: Disabled
    Main Oscillator Wait Time: 8163 cycles
    
  RA4M2 event data
  RA Common
    Main stack size (bytes): 0x400
    Heap size (bytes): 0x1000
    MCU Vcc (mV): 3300
    Parameter checking: Disabled
    Assert Failures: Return FSP_ERR_ASSERTION
    Error Log: No Error Log
    Clock Registers not Reset Values during Startup: Disabled
    Main Oscillator Populated: Populated
    PFS Protect: Enabled
    C Runtime Initialization : Enabled
    Early BSP Initialization : Disabled
    Main Oscillator Clock Source: Crystal or Resonator
    Subclock Populated: Populated
    Subclock Drive (Drive capacitance availability varies by MCU): Standard/Normal mode
    Subclock Stabilization Time (ms): 1000
    
  Clocks
    XTAL 24000000Hz
    HOCO 20MHz
    PLL Src: XTAL
    PLL Div /2
    PLL Mul x10.0
    PLL2 Src: XTAL
    PLL2 Div /2
    PLL2 Mul x20.0
    Clock Src: PLL
    CLKOUT Disabled
    UCLK Disabled
    ICLK Div /2
    PCLKA Div /2
    PCLKB Div /4
    PCLKC Div /4
    PCLKD Div /2
    FCLK Div /4
    CLKOUT Div /2
    UCLK Div /5
    
  Pin Configurations
    R7FA4M2AD3CFP.pincfg -> g_bsp_pin_cfg
      AVCC0 88 ANALOG0_AVCC0 - - - - - - - - IO "Read only" - 
      AVSS0 89 ANALOG0_AVSS0 - - - - - - - - IO "Read only" - 
      P000 100 - - - - Disabled - - "ADC0: AN000; ICU0: IRQ06" - None - - 
      P001 99 GPIO - - None "Output mode (Initial Low)" CMOS - "ADC0: AN001; ICU0: IRQ07" - IO - - 
      P002 98 GPIO - - None "Output mode (Initial Low)" CMOS - "ADC0: AN002; ICU0: IRQ08" - IO - - 
      P003 97 GPIO - - - "Output mode (Initial Low)" CMOS - "ADC0: AN003" - IO - - 
      P004 96 GPIO - - None "Output mode (Initial Low)" CMOS - "ADC0: AN004; ICU0: IRQ09" - IO - - 
      P005 95 GPIO - - None "Output mode (Initial Low)" CMOS - "ADC0: AN005; ICU0: IRQ10" - IO - - 
      P006 94 GPIO - - None "Output mode (Initial Low)" CMOS - "ADC0: AN006; ICU0: IRQ11" - IO - - 
      P007 93 - - - - Disabled - - "ADC0: AN007" - None - - 
      P008 92 - - - - Disabled - - "ADC0: AN008; ICU0: IRQ12" - None - - 
      P013 86 - - - - Disabled - - "ADC0: AN011; ANALOG0: VREFL" - None - - 
      P014 85 - - - - Disabled - - "ADC0: AN012; DAC0: DA0" - None - - 
      P015 84 - - - - Disabled - - "ADC0: AN013; DAC1: DA1; ICU0: IRQ13" - None - - 
      P100 75 SCI0_RXD0 - Low None "Peripheral mode" CMOS None "AGT0: AGTIO0; GPT_POEG0: GTETRGA; GPT5: GTIOC5B; ICU0: IRQ02; QSPI0: QSPCLK; SCI0: RXD0; SCI0: SCL0; SCI1: SCK1" - IO - - 
      P101 74 SCI0_TXD0 - Low None "Peripheral mode" CMOS None "AGT0: AGTEE0; GPT_POEG1: GTETRGB; GPT5: GTIOC5A; ICU0: IRQ01; QSPI0: QIO1; SCI0: SDA0; SCI0: TXD0; SCI1: CTSRTS1" - IO - - 
      P102 73 - - - - Disabled - - "ADC0: ADTRG0; AGT0: AGTO0; CAN0: CRX0; GPT_OPS0: GTOWLO; GPT2: GTIOC2B; QSPI0: QIO0; SCI0: SCK0" - None - - 
      P103 72 - - - - Disabled - - "AGT2: AGTIO2; CAN0: CTX0; GPT_OPS0: GTOWUP; GPT2: GTIOC2A; QSPI0: QIO3; SCI0: CTSRTS0" - None - - 
      P104 71 - - - - Disabled - - "AGT2: AGTEE2; GPT_POEG1: GTETRGB; GPT1: GTIOC1B; ICU0: IRQ01; QSPI0: QIO2" - None - - 
      P105 70 - - - - Disabled - - "AGT2: AGTO2; GPT_POEG0: GTETRGA; GPT1: GTIOC1A; ICU0: IRQ00" - None - - 
      P106 69 - - - - Disabled - - "AGT0: AGTOB0" - None - - 
      P107 68 - - - - Disabled - - "AGT0: AGTOA0" - None - - 
      P108 51 - - - - Disabled - - "AGT3: AGTOA3; DEBUG0: SWDIO; DEBUG0: TMS; GPT_OPS0: GTOULO; GPT0: GTIOC0B; SCI9: CTSRTS9; SPI0: SSLA0" - None - - 
      P109 52 - - - - Disabled - - "AGT3: AGTOB3; CGC0: CLKOUT; DEBUG0: TDO; DEBUG0: TRACESWO; GPT_OPS0: GTOVUP; GPT1: GTIOC1A; SCI9: SDA9; SCI9: TXD9; SPI0: MOSIA" - None - - 
      P110 53 - - - - Disabled - - "AGT3: AGTEE3; DEBUG0: TDI; GPT_OPS0: GTOVLO; GPT1: GTIOC1B; ICU0: IRQ03; SCI2: CTSRTS2; SCI9: RXD9; SCI9: SCL9; SPI0: MISOA" - None - - 
      P111 54 - - - - Disabled - - "AGT5: AGTOA5; GPT3: GTIOC3A; ICU0: IRQ04; SCI2: SCK2; SCI9: SCK9; SPI0: RSPCKA" - None - - 
      P112 55 SCI2_TXD2 - Low - "Peripheral mode" CMOS None "AGT5: AGTOB5; GPT3: GTIOC3B; QSPI0: QSSL; SCI1: SCK1; SCI2: SDA2; SCI2: TXD2; SPI0: SSLA0; SSI0: SSIBCK0" - IO - - 
      P113 56 SCI2_RXD2 - Low - "Peripheral mode" CMOS None "AGT5: AGTEE5; GPT2: GTIOC2A; SCI2: RXD2; SCI2: SCL2; SSI0: SSILRCK0" - IO - - 
      P114 57 - - - - Disabled - - "AGT5: AGTIO5; GPT2: GTIOC2B; SCI9: CTS9; SSI0: SSIRXD0" - None - - 
      P115 58 - - - - Disabled - - "GPT4: GTIOC4A; SSI0: SSITXD0" - None - - 
      P200 40 - - - - Disabled - - "ICU0: NMI" - None - - 
      P201 39 - - - - Disabled - - "SYSTEM0: MD" - None - - 
      P205 32 SCI4_TXD4 - Low None "Peripheral mode" CMOS None "AGT1: AGTO1; CGC0: CLKOUT; CTSU0: TS01; GPT_OPS0: GTIV; GPT4: GTIOC4A; ICU0: IRQ01; IIC1: SCL1; SCI4: SDA4; SCI4: TXD4; SCI9: CTSRTS9; SDHI0: SD0DAT3; SPI0: SSLA0; SSI0: SSILRCK0; USB_FS0: USB_OVRCURA" - IO - - 
      P206 31 SCI4_RXD4 - Low None "Peripheral mode" CMOS None "CTSU0: TS02; GPT_OPS0: GTIU; ICU0: IRQ00; IIC1: SDA1; SCI4: RXD4; SCI4: SCL4; SCI9: CTS9; SDHI0: SD0DAT2; SPI0: SSLA1; SSI0: SSIDATA0; USB_FS0: USB_VBUSEN" - IO - - 
      P207 30 - - - - Disabled - - "CTSU0: TSCAP; QSPI0: QSSL; SCI4: SDA4; SCI4: TXD4; SPI0: SSLA2" - None - - 
      P208 37 - - - - Disabled - - "DEBUG_TRACE0: TDATA3; GPT_OPS0: GTOVLO; QSPI0: QIO3; SDHI0: SD0DAT0" - None - - 
      P209 36 - - - - Disabled - - "AGT5: AGTEE5; DEBUG_TRACE0: TDATA2; GPT_OPS0: GTOVUP; QSPI0: QIO2; SDHI0: SD0WP" - None - - 
      P210 35 - - - - Disabled - - "AGT5: AGTOB5; DEBUG_TRACE0: TDATA1; GPT_OPS0: GTIW; QSPI0: QIO1; SDHI0: SD0CD" - None - - 
      P211 34 - - - - Disabled - - "AGT5: AGTOA5; DEBUG_TRACE0: TDATA0; GPT_OPS0: GTIV; QSPI0: QIO0; SDHI0: SD0CMD" - None - - 
      P212 14 - - - - Disabled - - "AGT1: AGTEE1; CGC0: EXTAL; GPT_POEG3: GTETRGD; GPT0: GTIOC0B; ICU0: IRQ03; SCI1: RXD1; SCI1: SCL1" - None - - 
      P213 13 - - - - Disabled - - "AGT2: AGTEE2; CGC0: XTAL; GPT_POEG2: GTETRGC; GPT0: GTIOC0A; ICU0: IRQ02; SCI1: SDA1; SCI1: TXD1" - None - - 
      P214 33 - - - - Disabled - - "AGT5: AGTO5; DEBUG_TRACE0: TCLK; GPT_OPS0: GTIU; QSPI0: QSPCLK; SDHI0: SD0CLK" - None - - 
      P300 50 - - - - Disabled - - "DEBUG0: SWCLK; DEBUG0: TCK; GPT_OPS0: GTOUUP; GPT0: GTIOC0A; SPI0: SSLA1" - None - - 
      P301 49 - - - - Disabled - - "AGT0: AGTIO0; GPT_OPS0: GTOULO; GPT4: GTIOC4B; ICU0: IRQ06; SCI2: RXD2; SCI2: SCL2; SCI9: CTSRTS9; SPI0: SSLA2" - None - - 
      P302 48 - - - - Disabled - - "GPT_OPS0: GTOUUP; GPT4: GTIOC4A; ICU0: IRQ05; SCI2: SDA2; SCI2: TXD2; SPI0: SSLA3" - None - - 
      P303 47 - - - - Disabled - - "GPT7: GTIOC7B; SCI9: CTS9" - None - - 
      P304 44 - - - - Disabled - - "AGT2: AGTEE2; GPT_OPS0: GTOWLO; GPT7: GTIOC7A; ICU0: IRQ09" - None - - 
      P305 43 - - - - Disabled - - "AGT2: AGTOB2; GPT_OPS0: GTOWUP; ICU0: IRQ08; QSPI0: QSPCLK" - None - - 
      P306 42 - - - - Disabled - - "AGT2: AGTOA2; GPT_OPS0: GTOULO; QSPI0: QSSL" - None - - 
      P307 41 - - - - Disabled - - "AGT4: AGTEE4; GPT_OPS0: GTOUUP; QSPI0: QIO0" - None - - 
      P400 1 SCI4_SCK4 - Low None "Peripheral mode" CMOS None "AGT1: AGTIO1; GPT6: GTIOC6A; ICU0: IRQ00; IIC0: SCL0; SCI4: SCK4; SSI_COMMON0: AUDIO_CLK" - IO - - 
      P401 2 - - - - Disabled - - "CAN0: CTX0; GPT_POEG0: GTETRGA; GPT6: GTIOC6B; ICU0: IRQ05; IIC0: SDA0; SCI4: CTSRTS4" - None - - 
      P402 3 - - - - Disabled - - "AGT0: AGTIO0; AGT1: AGTIO1; AGT2: AGTIO2; AGT3: AGTIO3; CAC0: CACREF; CAN0: CRX0; ICU0: IRQ04; RTC0: RTCIC0; SCI4: CTS4; SSI_COMMON0: AUDIO_CLK" - None - - 
      P403 4 - - - - Disabled - - "AGT0: AGTIO0; AGT1: AGTIO1; AGT2: AGTIO2; AGT3: AGTIO3; GPT3: GTIOC3A; ICU0: IRQ14; RTC0: RTCIC1; SSI0: SSIBCK0" - None - - 
      P404 5 - - - - Disabled - - "AGT0: AGTIO0; AGT1: AGTIO1; AGT2: AGTIO2; AGT3: AGTIO3; GPT3: GTIOC3B; ICU0: IRQ15; RTC0: RTCIC2; SSI0: SSILRCK0" - None - - 
      P405 6 - - - - Disabled - - "GPT1: GTIOC1A; SSI0: SSITXD0" - None - - 
      P406 7 - - - - Disabled - - "AGT5: AGTO5; GPT1: GTIOC1B; SPI0: SSLA3; SSI0: SSIRXD0" - None - - 
      P407 25 - - - - Disabled - - "ADC0: ADTRG0; AGT0: AGTIO0; CTSU0: TS03; GPT6: GTIOC6A; IIC0: SDA0; RTC0: RTCOUT; SCI4: CTSRTS4; SPI0: SSLA3; USB_FS0: USB_VBUS" - None - - 
      P408 24 SCI3_RXD3 - Low None "Peripheral mode" CMOS None "AGT2: AGTOB2; CTSU0: TS04; GPT_OPS0: GTOWLO; GPT6: GTIOC6B; ICU0: IRQ07; IIC0: SCL0; SCI3: RXD3; SCI3: SCL3; SCI4: CTS4; USB_FS0: USB_ID" - IO - - 
      P409 23 SCI3_TXD3 - Low None "Peripheral mode" CMOS None "AGT2: AGTOA2; CTSU0: TS05; GPT_OPS0: GTOWUP; ICU0: IRQ06; SCI3: SDA3; SCI3: TXD3; USB_FS0: USB_EXICEN" - IO - - 
      P410 22 - - - - Disabled - - "AGT1: AGTOB1; CTSU0: TS06; GPT_OPS0: GTOVLO; ICU0: IRQ05; SCI0: RXD0; SCI0: SCL0; SCI3: SCK3; SDHI0: SD0DAT1" - None - - 
      P411 21 - - - - Disabled - - "AGT1: AGTOA1; CTSU0: TS07; GPT_OPS0: GTOVUP; ICU0: IRQ04; SCI0: SDA0; SCI0: TXD0; SCI3: CTSRTS3; SDHI0: SD0DAT0" - None - - 
      P412 20 - - - - Disabled - - "AGT1: AGTEE1; CTSU0: TS08; GPT_OPS0: GTOULO; SCI0: SCK0; SCI3: CTS3; SDHI0: SD0CMD" - None - - 
      P413 19 - - - - Disabled - - "AGT3: AGTEE3; CTSU0: TS09; GPT_OPS0: GTOUUP; SCI0: CTSRTS0; SDHI0: SD0CLK" - None - - 
      P414 18 - - - - Disabled - - "AGT5: AGTIO5; CTSU0: TS10; GPT0: GTIOC0B; ICU0: IRQ09; SCI0: CTS0; SDHI0: SD0WP" - None - - 
      P415 17 - - - - Disabled - - "AGT4: AGTIO4; CTSU0: TS11; GPT0: GTIOC0A; ICU0: IRQ08; SDHI0: SD0CD; USB_FS0: USB_VBUSEN" - None - - 
      P500 76 - - - - Disabled - - "ADC0: AN016; AGT0: AGTOA0; CAC0: CACREF; GPT_OPS0: GTIU; QSPI0: QSPCLK; USB_FS0: USB_VBUSEN" - None - - 
      P501 77 - - - - Disabled - - "AGT0: AGTOB0; GPT_OPS0: GTIV; ICU0: IRQ11; QSPI0: QSSL; USB_FS0: USB_OVRCURA" - None - - 
      P502 78 - - - - Disabled - - "AGT2: AGTOA2; GPT_OPS0: GTIW; ICU0: IRQ12; QSPI0: QIO0; USB_FS0: USB_OVRCURB" - None - - 
      P503 79 - - - - Disabled - - "AGT2: AGTOB2; GPT_POEG2: GTETRGC; QSPI0: QIO1; USB_FS0: USB_EXICEN" - None - - 
      P504 80 - - - - Disabled - - "AGT3: AGTOA3; GPT_POEG3: GTETRGD; QSPI0: QIO2; USB_FS0: USB_ID" - None - - 
      P505 81 - - - - Disabled - - "AGT3: AGTOB3; ICU0: IRQ14; QSPI0: QIO3" - None - - 
      P600 67 - - - - Disabled - - "AGT3: AGTIO3; CAC0: CACREF; CGC0: CLKOUT; GPT6: GTIOC6B; SCI9: SCK9" - None - - 
      P601 66 SCI9_RXD9 - Low - "Peripheral mode" CMOS None "AGT3: AGTEE3; GPT6: GTIOC6A; SCI9: RXD9; SCI9: SCL9" - IO - - 
      P602 65 SCI9_TXD9 - Low - "Peripheral mode" CMOS None "AGT3: AGTO3; GPT7: GTIOC7B; SCI9: SDA9; SCI9: TXD9" - IO - - 
      P603 64 - - - - Disabled - - "AGT4: AGTIO4; GPT7: GTIOC7A; SCI9: CTSRTS9" - None - - 
      P608 59 GPIO - Low - "Output mode (Initial High)" CMOS - "GPT4: GTIOC4B" - IO - - 
      P609 60 GPIO - Low - "Output mode (Initial High)" CMOS - "AGT5: AGTO5; GPT5: GTIOC5A" - IO - - 
      P610 61 GPIO - Low - "Output mode (Initial High)" CMOS - "AGT4: AGTO4; GPT5: GTIOC5B" - IO - - 
      P708 16 - - - - Disabled - - "CAC0: CACREF; CTSU0: TS12; ICU0: IRQ11; SCI1: RXD1; SCI1: SCL1; SSI_COMMON0: AUDIO_CLK" - None - - 
      RES 38 SYSTEM0_RES - - - - - - - - IO "Read only" - 
      USBDM 27 USB_FS0_USB_DM - - - - - - - - IO "Read only" - 
      USBDP 28 USB_FS0_USB_DP - - - - - - - - IO "Read only" - 
      VBATT 8 SYSTEM0_VBATT - - - - - - - - IO "Read only" - 
      VCC 15 SYSTEM0_VCC - - - - - - - - IO "Read only" - 
      VCC 46 SYSTEM0_VCC - - - - - - - - IO "Read only" - 
      VCC 62 SYSTEM0_VCC - - - - - - - - IO "Read only" - 
      VCC 82 SYSTEM0_VCC - - - - - - - - IO "Read only" - 
      VCCUSB 29 USB_FS0_VCC_USB - - - - - - - - IO "Read only" - 
      VCL0 9 SYSTEM0_VCL0 - - - - - - - - IO "Read only" - 
      VREFH 87 ANALOG0_VREFH - - - - - - - - IO "Read only" - 
      VREFH0 91 ANALOG0_VREFH0 - - - - - - - - IO "Read only" - 
      VREFL0 90 ANALOG0_VREFL0 - - - - - - - - IO "Read only" - 
      VSS 12 SYSTEM0_VSS - - - - - - - - IO "Read only" - 
      VSS 45 SYSTEM0_VSS - - - - - - - - IO "Read only" - 
      VSS 63 SYSTEM0_VSS - - - - - - - - IO "Read only" - 
      VSS 83 SYSTEM0_VSS - - - - - - - - IO "Read only" - 
      VSSUSB 26 USB_FS0_VSS_USB - - - - - - - - IO "Read only" - 
      XCIN 10 CGC0_XCIN - - - - - - - - IO "Read only" - 
      XCOUT 11 CGC0_XCOUT - - - - - - - - IO "Read only" - 
    
  User Events
    
  User Event Links
    
  Module "I/O Port (r_ioport)"
    Parameter Checking: Default (BSP)
    
  Module "SPI (r_sci_spi)"
    Parameter Checking: Default (BSP)
    DTC Support: Enabled
    
  Module "Transfer (r_dtc)"
    Parameter Checking: Default (BSP)
    Linker section to keep DTC vector table: .fsp_dtc_vector_table
    
  Module "UART (r_sci_uart)"
    Parameter Checking: Default (BSP)
    FIFO Support: Disable
    DTC Support: Disable
    Flow Control Support: Disable
    RS-485 Support: Disable
    
  HAL
    Instance "g_ioport I/O Port (r_ioport)"
      Name: g_ioport
      1st Port ELC Trigger Source: Disabled
      2nd Port ELC Trigger Source: Disabled
      3rd Port ELC Trigger Source: Disabled
      4th Port ELC Trigger Source: Disabled
      Pin Configuration Name: g_bsp_pin_cfg
      
    Instance "g_spi9 SPI (r_sci_spi)"
      Name: g_spi9
      Channel: 9
      Operating Mode: Master
      Clock Phase: Data sampling on odd edge, data variation on even edge
      Clock Polarity: Low when idle
      Mode Fault Error: Disable
      Bit Order: MSB First
      Callback: sci_spi_callback
      Receive Interrupt Priority: Priority 12
      Transmit Interrupt Priority: Priority 12
      Transmit End Interrupt Priority: Priority 12
      Error Interrupt Priority: Priority 12
      Bitrate: 7500000
      Bitrate Modulation: Disabled
      
      Instance "g_transfer0 Transfer (r_dtc) SCI9 TXI (Transmit data empty)"
        Name: g_transfer0
        Mode: Normal
        Transfer Size: 1 Byte
        Destination Address Mode: Fixed
        Source Address Mode: Incremented
        Repeat Area (Unused in Normal Mode): Source
        Interrupt Frequency: After all transfers have completed
        Number of Transfers: 0
        Number of Blocks (Valid only in Block Mode): 0
        Number of Transfer Descriptors: 1
        Activation Source: SCI9 TXI (Transmit data empty)
        
      Instance "g_transfer1 Transfer (r_dtc) SCI9 RXI (Receive data full)"
        Name: g_transfer1
        Mode: Normal
        Transfer Size: 1 Byte
        Destination Address Mode: Incremented
        Source Address Mode: Fixed
        Repeat Area (Unused in Normal Mode): Destination
        Interrupt Frequency: After all transfers have completed
        Number of Transfers: 0
        Number of Blocks (Valid only in Block Mode): 0
        Number of Transfer Descriptors: 1
        Activation Source: SCI9 RXI (Receive data full)
        
    Instance "g_uart0 UART (r_sci_uart)"
      General: Name: g_uart0
      General: Channel: 0
      General: Data Bits: 8bits
      General: Parity: None
      General: Stop Bits: 1bit
      Baud: Baud Rate: 115200
      Baud: Baud Rate Modulation: Disabled
      Baud: Max Error (%): 5
      Flow Control: CTS/RTS Selection: Hardware RTS
      Flow Control: Software RTS Port: Disabled
      Flow Control: Software RTS Pin: Disabled
      Extra: Clock Source: Internal Clock
      Extra: Start bit detection: Falling Edge
      Extra: Noise Filter: Disable
      Extra: Receive FIFO Trigger Level: Max
      Extra: RS-485: DE Pin: Disable
      Extra: RS-485: DE Pin Polarity: Active High
      Extra: RS-485: DE Port Number: Disabled
      Extra: RS-485: DE Pin Number: Disabled
      Interrupts: Callback: debug_uart0_callback
      Interrupts: Receive Interrupt Priority: Priority 12
      Interrupts: Transmit Data Empty Interrupt Priority: Priority 12
      Interrupts: Transmit End Interrupt Priority: Priority 12
      Interrupts: Error Interrupt Priority: Priority 12
      
    Instance "g_uart2_esp8266 UART (r_sci_uart)"
      General: Name: g_uart2_esp8266
      General: Channel: 2
      General: Data Bits: 8bits
      General: Parity: None
      General: Stop Bits: 1bit
      Baud: Baud Rate: 115200
      Baud: Baud Rate Modulation: Disabled
      Baud: Max Error (%): 5
      Flow Control: CTS/RTS Selection: Hardware RTS
      Flow Control: Software RTS Port: Disabled
      Flow Control: Software RTS Pin: Disabled
      Extra: Clock Source: Internal Clock
      Extra: Start bit detection: Falling Edge
      Extra: Noise Filter: Disable
      Extra: Receive FIFO Trigger Level: Max
      Extra: RS-485: DE Pin: Disable
      Extra: RS-485: DE Pin Polarity: Active High
      Extra: RS-485: DE Port Number: Disabled
      Extra: RS-485: DE Pin Number: Disabled
      Interrupts: Callback: esp8266_uart2_callback
      Interrupts: Receive Interrupt Priority: Priority 12
      Interrupts: Transmit Data Empty Interrupt Priority: Priority 12
      Interrupts: Transmit End Interrupt Priority: Priority 12
      Interrupts: Error Interrupt Priority: Priority 12
      
